MSO71604

Tektronix MSO71604 Oscilloscope

The Tektronix Oscilloscope model MSO71604 has precise, easy, and Customizable Physical Layer Certification Testing for engineers with industry-standard accreditation needs, standard-particular consistence and investigation modules that arrange the pass/fall flat waveform cover and estimation restrain testing. Modules are accessible for PCI Express®, DDR Memory, Serial ATA, SAS, HDMI, Ethernet, Display Port, MIPI®C-PHY, MIPI®D-PHY and M-PHY, Power Supplies, and USB.

MSO71604 includes a DDR Memory Bus Analysis (Option DDRA), that automatically distinguishes DDR1, LPDDR, LPDDR2, LPDDR3, DDR2, DDR3, DDR4, and GDDR3 that reads, writes and makes JEDEC conformance estimations with pass/fail outcomes on all edges in each Read and Write burst. DDRA gives estimations of clock, address, and control signals. Notwithstanding empowering conformance testing DDRA with DPOJET is the quickest approach to troubleshoot complex memory flagging issues. DDRA can likewise utilize the Command/Address lines to trigger particular read/compose states when running on the MSO70000 Series Mixed Signal Oscilloscope, which offers 16 channels of advanced rationale examining.

This model includes a C-PHY, which utilizes a novel component for clock recuperation. C-PHY 1.0 actualizes a custom clock recuperation calculation known as triggered eye. In this model, the initial zero intersection of the four differential signs is utilized as a trigger point for clock recuperation and rendering the eye outline. Using the activated eye component, the jitter at the trigger point (zero intersection) is analyzed and thought about the opposite side. Jitter and eye chart rendering performed over the whole record length enables originators to better portray gadgets by showing inconsistencies of the gadget over an expanded timeframe.

You can check the manual for this model on the